The present inventive concept relates to a memory device with reduced operating current.
As the size of memory devices has increased so as to provide increased storage capacity, bit lines and word lines connected with memory cells may be disposed as having a hierarchical structure. For example, a bit line may include a global bit line and a plurality of local bit lines connected with the global bit line. A word line may include a main word line and a plurality of sub-word lines connected with the main word line.
In such cases, distances between a read circuit and a write circuit, and a memory cell may be significantly increased. As a result, capacitance of bit lines may also be relatively large. Further, the amount of current required for charging and discharging a bit line may also be relatively large. For example, a memory device in which hundreds of read circuits simultaneously operate may require current of hundreds of mA in order to charge a plurality of bit lines for each read operation. The current consumption may deteriorate current performance of memory and generate power noise.